According to the prior art various technologies are used for the manufacturing of VDMOS transistors. A single VDMOS cell as a base element of the VDMOS transistors is sufficiently exhaustively described in the literature and is considered as well known. A substantial part of the manufacturing process is the contacting of a composite of VDMOS cells, in particular the manner of contacting the gate electrode.
VDMOS cells are contacted at three locations. Firstly on the wafer back side or chip back side (across wide areas), respectively, and on the other hand at the wafer surface or chip surface at a restricted contact location. At the wafer surface or chip surface the gate and source/body contacts have to be realized. Both contact types of the wafer surface or chip surface require respective mask layers. In some technologies the source/body contact is fabricated by solely etching into the single-crystalline silicon. In this case, the usage of only one mask layer for both contact hole types is difficult. The problem resides in the fact that during the plasma etch process both contact hole types, i.e. the gate and the source/body contacts, are etched simultaneously. The depth of the etching of the source/body contact into the silicon is approximately of the same order of magnitude as the thickness of the polysilicon layer below the gate contact (about 0.3 micrometers to 0.5 micrometers), which is the electrical connection of the gate. At the end of the plasma etch process the layer thickness of the polysilicon in the area of the gate contact hole region approaches zero. On the other hand, for the source region it is also necessary to reduce the interlayer dielectric in the contact hole with respect to its lateral extension to a certain degree to obtain a sufficient contact. During this wet chemical etch process the source contact hole is enlarged towards the gate. This process is sufficiently described. The disadvantage of this technique resides in the fact that with the polysilicon being fully or partially removed in the gate contact hole the field oxide may be etched within the gate contact hole simultaneously. The etch process attacks the field oxide in the depth and under etches the polysilicon. In this manner, a deformed gate contact is formed, thereby possibly resulting in later consequences with respect to the reliability of the transistors. In U.S. Pat. No. 6,025,646 in FIG. 3d a deformed gate contact (detail 27b) is illustrated in a schematic manner.